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| NTHD4502N Power MOSFET 30 V, 3.9 A, Dual N-Channel ChipFETt Features * Planar Technology Device Offers Low RDS(on) and Fast Switching Speed * Leadless ChipFET Package has 40% Smaller Footprint than TSOP-6. * ChipFET Package Exhibits Excellent Thermal Capabilities. Ideal for * Applications Where Heat Transfer is Required. Pb-Free Package is Available V(BR)DSS 30 V 110 mW @ 4.5 V Ideal Device for Applications Where Board Space is at a Premium. http://onsemi.com RDS(on) TYP 80 mW @ 10 V 3.9 A ID MAX Applications * DC-DC Buck or Boost Converters * Low Side Switching * Optimized for Battery and Low Side Switching Applications in Computing and Portable Equipment MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) Steady State t5s Power Dissipation (Note 1) Steady State t5s Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current ESD Capability (Note 3) TA = 25C TA = 85C TA = 25C PD TA = 25C 25 C 2.1 TA = 25C Steady y State TA = 85C TA = 25C PD IDM ESD- HBM TJ, TSTG IS TL ID 2.2 1.6 0.64 12 125 -55 to 150 2.5 260 W A V C A C A Symbol VDSS VGS ID Value 30 20 2.9 2.1 3.9 1.13 W Unit V V A D1, D2 G 1 , G2 S1, S2 N-Channel MOSFET ChipFET CASE 1206A STYLE 2 PIN CONNECTIONS D1 8 D1 7 D2 6 D2 5 1 S1 2 G1 3 S2 4 G2 1 2 3 4 MARKING DIAGRAM 8 7 6 5 C5 M tp = 10 ms C = 100 pF, RS = 1500 W Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8" from case for 10 s) C5 = Specific Device Code M = Month Code Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface Mounted on FR4 Board using the minimum recommended pad size (Cu area = 0.214 in sq). 3. ESD Rating Information: HBM Class 0. ORDERING INFORMATION Device NTHD4502NT1 NTHD4502NT1G Package ChipFET ChipFET (Pb-Free) Shipping 3000/Tape & Reel 3000/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2004 1 October, 2004 - Rev. 4 Publication Order Number: NTHD4502N/D NTHD4502N THERMAL RESISTANCE RATINGS Parameter Junction-to-Ambient - Steady State (Note 4) Junction-to-Ambient - t 5 s (Note 4) Junction-to-Ambient - Steady State (Note 5) Symbol RqJA RqJA RqJA Max 110 60 195 Unit C/W 4. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 5. Surface Mounted on FR4 Board using the minimum recommended pad size (Cu area = 0.214 in sq). ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Zero Gate Voltage Drain Current V(BR)DSS IDSS VGS = 0 V, ID = 250 mA VGS = 0 V, VDS = 24 V VGS = 0 V, VDS = 24 V, TJ = 125C Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 6) Gate Threshold Voltage Drain-to-Source On-Resistance VGS(TH) RDS(on) () VGS = VDS, ID = 250 mA VGS = 10 V, ID = 2.9 A VGS = 4.5 V, ID = 2.2 A Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge CISS COSS CRSS CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) QG(TH) QGS QGD VGS = 4.5 V, VDS = 24 V, ID = 2.9 A VGS = 10 V, VDS = 15 V, ID = 2.9 A VGS = 0 V, f = 1.0 MHz, VDS = 24 V VGS = 0 V, f = 1.0 MHz, VDS = 15 V 140 53 16 135 42 13 3.6 0.3 0.6 0.7 1.9 0.3 0.6 0.9 nC 250 75 25 7.0 nC pF pF gFS VDS = 15 V, ID = 2.9 A 1.0 1.65 78 105 3.8 3.0 85 140 S V mW IGSS VDS = 0 V, VGS = "20 V 30 36 1.0 10 "100 nA V mA Symbol Test Conditions Min Typ Max Units 6. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. http://onsemi.com 2 NTHD4502N ELECTRICAL CHARACTERISTICS (continued) (TJ = 25C unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Time Reverse Recovery Charge SWITCHING CHARACTERISTICS (Note 7) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time td(ON) tr td(OFF) tf td(ON) tr td(OFF) tf VGS = 4.5 V, VDD = 24 V, ID = 2.9 A, RG = 2.5 W VGS = 10 V, VDD = 24 V, ID = 1 A, RG = 6 W 6.5 5.4 14.9 1.8 7.8 12.6 9.6 2.8 12 10 25 5.0 ns ns VSD tRR QRR tRR QRR VGS = 0 V, IS = 2.5 A VGS = 0 V, IS = 2.9 A, dIS/dt = 100 A/ms VGS = 0 V, IS = 1.0 A, dIS/dt = 100 A/ms 0.85 8.6 4.0 8.4 4.0 1.2 V ns nC ns nC 7. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTHD4502N TYPICAL PERFORMANCE CURVES 10 VGS = 10, 6, 5, 4.5 & 4.2 V resp. ID, DRAIN CURRENT (AMPS) 8 4V ID, DRAIN CURRENT (AMPS) 3.8 V 3.6 V 6 3.4 V 4 TJ = 25C 2 0 0 1 2 3 4 5 3.2 V 3V 2.8 V 2.6 V 6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 5 4 3 2 1 0 1 25C TJ = -55C 3 2 4 5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6 100C 6 VDS 10 V Figure 1. On-Region Characteristics RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.3 0.25 0.2 0.15 0.1 0.05 0 2 3 8 9 4 5 6 7 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 ID = 2.9 A TJ = 25C 0.12 Figure 2. Transfer Characteristics TJ = 25C 0.11 VGS = 4.5 V 0.10 0.09 VGS = 10 V 0.08 0.07 2 3 4 5 6 ID, DRAIN CURRENT (AMPS) Figure 3. On-Resistance vs. Gate-to-Source Voltage 1.8 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.6 1.4 1.2 1.0 0.8 0.6 -50 0.1 -25 0 25 50 75 100 125 150 ID = 2.9 A VGS = 10 V IDSS, LEAKAGE (nA) 100 1000 Figure 4. On-Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150C 10 TJ = 100C 1 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-to-Source Leakage Current vs. Voltage http://onsemi.com 4 NTHD4502N TYPICAL PERFORMANCE CURVES 300 12 10 8 6 4 2 0 0 1 2 3 QG, TOTAL GATE CHARGE (nC) 4 QGS QGD ID = 2.9 A TJ = 25C VDS VGS 12 8 4 0 QG 24 20 16 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS = 0 V CISS VGS = 0 V TJ = 25C C, CAPACITANCE (pF) 200 CRSS 100 COSS 0 10 5 VGS 0 VDS 5 10 15 20 25 30 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 100 IS, SOURCE CURRENT (AMPS) 3 Figure 8. Gate-to-Source and Drain-to-Source Voltage vs. Total Charge VGS = 0 V TJ = 25C t, TIME (ns) 10 td(off) td(on) tr 2 1 tf VDD = 24 V ID = 1.0 A VGS = 10 V 1 10 RG, GATE RESISTANCE (OHMS) 100 1 0.1 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 5 NTHD4502N PACKAGE DIMENSIONS ChipFET] CASE 1206A-03 ISSUE E A 8 7 6 5 M K 5 6 3 7 2 8 1 S 1 2 3 4 B 4 L G D J STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A-01 AND 1206A-02 OBSOLETE. NEW STANDARD IS 1206A-03. DIM A B C D G J K L M S MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 NOM 1.80 2.00 INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 NOM 0.072 0.080 C 0.05 (0.002) SOLDERING FOOTPRINT* 2.032 0.08 0.457 0.018 0.635 0.025 0.635 0.025 1.092 0.043 2.032 0.08 0.178 0.007 0.457 0.018 0.711 0.028 0.66 0.026 SCALE 20:1 mm inches 0.66 0.026 0.254 0.010 SCALE 20:1 mm inches Basic *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ChipFET is a trademark of Vishay Siliconix. Style 2 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 6 NTHD4502N/D |
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